The lanes become less important when the bandwidth is so large. With PCIe 5 you'd have a tough time saturating it.
This. 24 lanes of pcie 5 is 48 lanes of pcie 4, though pcie 5 components are pretty slim pickings.
How does a 4 lane pcie 5 slot look to a pcie 4 device? Ex: if you put a 3080ti in a pcie 5 4x slot, how much bandwidth does it get?
The thing is, unless you use some sort of PLX chip you can't pool all that bandwidth.
If you stick a 8x gen 1 device in an 8x gen5 slot, it still uses all 8x lanes, even if it is just operating in gen 1 mode, and a fraction (~1/16) of the max bandwidth those Gen 5 lanes offer.
Gen 5 devices are almost non-existent on the market today. Even gen 4 devices are rare outside of GPU's and certain high end NVMe SSD's
Most expansion cards you are going to wind up buying are going to be Gen 3 or Gen 2. Some may even be Gen 1. Heck, if an old sound device works fine on 1x gen 1, why redesign it?
And that's the problem. 24x lanes of Gen5 is an absolutely massive amount of bandwidth, but you can't really make the most of it without some sort of PLX chip that helps keep the lanes to the CPU maxxed at gen 5 speeds and pools that bandwidth and divy's it up across devices and slots of different generations.
The problem is PLX chips are expensive, add power consumption, and most importantly cause added latency on the PCIe bus, which is detrimental to performance, which is why we see so few motherboards use them.
So, what does this mean in practice?
Since most of us use 16x capable discrete GPU's, and don't want to risk them losing an ounce of performance (even though in general 8x is probably fine) we are going to seek to have them maxed out at 16x.
So, 16/24 goes to the GPU, and any GPU today is probably only using half the potential bandwidth of those 16x lanes, since it is only Gen4, but the 16x lanes are used none the less, because the protocol negotiates the speed at the lower of the capabilities of the host and the GPU. 8x Gen5 may provide the same amount of bandwidth as 16x Gen4, but the GPU can't do anything with 8x Gen5, if it fdrops to 8x, it will be getting 8x Gen4 bandwidth, so it runs at 16x gen4, and uses all 16 of those lanes.
So, once the GPU is out of the way we have 24-16 = 8 lanes left.
4 of those lanes are going to go to an NVMe device. Again, just like with the GPU it is going to use all lanes, even though it can't connect with the latest gen protocol.
Now we have 4 lanes left. These are all going to go to the chipset.
The chipset is ironically the only device in the system that makes good use of the lanes. At least in cases where the motherboard and CPU are at the same generation (backwards compatibility sometimes allows you to stick a newer CPU into an older motherboard, in which case, the chipset lanes will only connect at the older PCIe gen standard) They uses some sort of internal PLX like capability to spread out the total 4x Gen5 bandwidth over all on board devices, and in some designs share whatever bandwidth is left over to some extra PCIe slots or secondary m.2 slot. These are nice to have, but again, PLX=Latency, and that reduces performance.
So I guess my point is, the total bandwidth really doesn't matter. Unless something changes about how these things work, you could have gen 30 PCIe bandwidth, and those 24 lanes will still be too restrictive. Gen 5 has some pretty impressive raw bandwidth numbers, but the way backwards compatibility and PCIe lanes works means in most cases it is simply not usable for anyhting but the bare minimum 1 GPU and 1 NVMe drive.
