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At today's HPC Developer Conference, Intel disclosed quite a bit about its new Xe architecture and first exascale GPU, codenamed "Ponte Vecchio." This will be a 7 nm part that leverages the power of chiplets with EMIB (a chip-to-chip interconnect technology) and Foveros, a 3D-stacking technique for joining different chips together. Ponte Vecchio will debut in the Aurora supercomputer, which will be installed at the Argonne National Laboratory in 2021.
Koduri has explained that Intel will have a single ‘Xe’ architecture but multiple sub-architectures / microarchitectures (or however you want to characterize it in a GPU) in order to address different parts of the market. The ultra-mobile parts of the product stack might focus on small die size and high efficiency libraries, whereas a compute product might have high double-precision performance and run high-performance libraries.
Koduri has explained that Intel will have a single ‘Xe’ architecture but multiple sub-architectures / microarchitectures (or however you want to characterize it in a GPU) in order to address different parts of the market. The ultra-mobile parts of the product stack might focus on small die size and high efficiency libraries, whereas a compute product might have high double-precision performance and run high-performance libraries.