AMD Zen 6 Discussion

David_Schroth

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Sorry, it's an old Anandtech in joke 🙂 I absolutely don't expect SMT4, because at that point you start adding more resources prioritising SMT to the detriment of per-core performance. There's some utility as a licensing hack for software that is charged per core, rather than per thread, but that's a serious niche.

I do wonder what level of single thread performance we'll get at reasonable cache sizes and clock speeds. Just from the timing, I expect to see Zen 6 in the next generation of consoles, so it's probably going to set the gaming baseline performance level for the next 10 years.
 
Maybe don't expect 7 GHz. It'll probably be something more conservative than that. There's still a lot we don't know. Perhaps if some of the acerbic leakers follow us over here we can get a repeat of stuff leaked/teased elsewhere. Or people can just mine the Zen6 speculation thread from AT for fodder.

That being said, it would be very sad if Medusa Halo doesn't become a thing. An upgraded Strix Halo sounds kinda neat actually.
 
Maybe don't expect 7 GHz. It'll probably be something more conservative than that. There's still a lot we don't know. Perhaps if some of the acerbic leakers follow us over here we can get a repeat of stuff leaked/teased elsewhere. Or people can just mine the Zen6 speculation thread from AT for fodder.

That being said, it would be very sad if Medusa Halo doesn't become a thing. An upgraded Strix Halo sounds kinda neat actually.
The ceiling for single-core (maybe even two CPU cores boost)will probably be around 6.5-6.7ghz. This refers to the strongest or best Zen 6 CPU-s.
 
Overclockers are currently hitting ~5.8GHz using bus clock and BIOS trickery on the best Zen 5 samples they can find (including X3D variants). AMD could easily stabilize higher clockspeeds by design IMO. 6.0GHz as a stock all-core might be reasonable for top-end samples.

Much more interested in a new memory controller though, personally. With 12 cores per CCD, they're going to need to get >DDR5-8000 stable across the board, i.e. out of the box with EXPO. I assume CUDIMM support will be included and help with this.
 
I just want 12 cores per CCD with more L3 on the CCD. Hopefully its not a 1:1 ratio on the increase and we get a little bump in L3 too.
 
and a little more memory speed with less latency....
They'd need to abandon their multi-CCD configuration that adds another interconnect stage if they want to drop latency any significant amount really.
 
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