AMD Zen 6 Discussion

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David_Schroth

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Sorry, it's an old Anandtech in joke 🙂 I absolutely don't expect SMT4, because at that point you start adding more resources prioritising SMT to the detriment of per-core performance. There's some utility as a licensing hack for software that is charged per core, rather than per thread, but that's a serious niche.

I do wonder what level of single thread performance we'll get at reasonable cache sizes and clock speeds. Just from the timing, I expect to see Zen 6 in the next generation of consoles, so it's probably going to set the gaming baseline performance level for the next 10 years.
 
Maybe don't expect 7 GHz. It'll probably be something more conservative than that. There's still a lot we don't know. Perhaps if some of the acerbic leakers follow us over here we can get a repeat of stuff leaked/teased elsewhere. Or people can just mine the Zen6 speculation thread from AT for fodder.

That being said, it would be very sad if Medusa Halo doesn't become a thing. An upgraded Strix Halo sounds kinda neat actually.
 
DrMrLordX said:
Maybe don't expect 7 GHz. It'll probably be something more conservative than that. There's still a lot we don't know. Perhaps if some of the acerbic leakers follow us over here we can get a repeat of stuff leaked/teased elsewhere. Or people can just mine the Zen6 speculation thread from AT for fodder.

That being said, it would be very sad if Medusa Halo doesn't become a thing. An upgraded Strix Halo sounds kinda neat actually.
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The ceiling for single-core (maybe even two CPU cores boost)will probably be around 6.5-6.7ghz. This refers to the strongest or best Zen 6 CPU-s.
 
Overclockers are currently hitting ~5.8GHz using bus clock and BIOS trickery on the best Zen 5 samples they can find (including X3D variants). AMD could easily stabilize higher clockspeeds by design IMO. 6.0GHz as a stock all-core might be reasonable for top-end samples.

Much more interested in a new memory controller though, personally. With 12 cores per CCD, they're going to need to get >DDR5-8000 stable across the board, i.e. out of the box with EXPO. I assume CUDIMM support will be included and help with this.
 
I just want 12 cores per CCD with more L3 on the CCD. Hopefully its not a 1:1 ratio on the increase and we get a little bump in L3 too.
 
LazyGamer said:
They'd need to abandon their multi-CCD configuration that adds another interconnect stage if they want to drop latency any significant amount really.
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I'm not going to armchair engineer the CPU's... not like back in the 90's when PC magazine deep dove into CPU design. Sigh.. I miss that mag.

Where was I... this isn't my house... WHO ARE YOU! STRANGER DANGER!!! STOP DROP AND ROLL..


Ok anyway I just think they need to find a better way of utilizing the memory and doing the interconnects better between CCD's. I'm of a mind that for those of us that WANT the big core counts for desktop use we will require the CCD's to be there. They save on cost in making them because you don't run the risk of bad silicone when you pack less into each CCD. (Meaning your failures are not as impactful) As it is going to 12 cores per CCD is a 50% pump in the top line, I expect to see at least a 30% cost increase for those top line CPU's.

And the interconnect issue should have a better solve as well, such as a fiber optic or light path traces between the CCD's. And a higher speed better designed interconnect. Don't forget that historically for these Ryzen CPU's at least, the interconnect and I/O controllers are a larger technology set altogether. It's distinctly possible with going to a smaller node with a bit better technology they can decrease trace sizes and increase throughput of the controllers and interconnects while still saving cost per CPU.

But I'm not that type of Engineer. IT's outside of my purview just making some logical statements based on observations and information that has stuck in my mind... for now.
 
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