AMD’s 3rd Gen Threadripper CPUs Could Be Coming This October

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A new report by DigiTimes suggests that AMD could be crashing Intel's HEDT party in October with its third-generation Threadripper chips, which bring up to 64 cores. Intel's Cascade Lake-X parts, running on the Glacial Falls platform, top out at 36 cores.

A new chipset with PCIe 4.0 seems inevitable, but enthusiasts who wish to stick with their current TR4 motherboards should be able to do so with a BIOS update that adds support for the Zen 2-based Threadripper range.

AMD has the option to deploy up to 64 CPU cores across eight 7 nm "Zen 2" chiplets, while the 12 nm I/O controller die will be likely reconfigured for the HEDT platform with a monolithic 4-channel DDR4 memory interface and 64 PCIe gen 4.0 lanes. It's capable of 8 memory channels on the 2nd generation EPYC.
 
Hmm. Maybe I won't be buying a 3950x after all.

Would be sweet to have all those PCIe lanes, if they only make one that has high clocks, isn't in crazy-land from a core count perspective and isn't prohibitively expensive.

I can't keep putting off my upgrade though, at least not without firm non-rumor information. There is always something better just around the corner, and my CPU is 8 years old now. If we don't have more confirmed information by the time the 3950x launches, I'll probably just buy one. It appears to do what I need it to, and have enough PCIe lanes when coupled with the x570 chipset (albeit only barely)
 
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I want a newer CPU, but I may hold off and wait for these newer Threadrippers before making a decision on what route to go.
 
I want a newer CPU, but I may hold off and wait for these newer Threadrippers before making a decision on what route to go.

I'm inclined to do the same, but by the time the new TR's are out, there may be something else around the corner. If you always wait for the next great thing, you never buy anything.

I'd very much like a TR with all those PCIe lanes, but at a minimum it would have to be clocked as high as the 3950x, and I'm unlikely to buy anything withore than 16 cores. Even that is already way more than I have any need for.
 
May ditch the Asrock and 1900x to put toward an upgrade to the MSI board.
 
I'm looking to build a new rig later this year, but I'm not going to wait around for TR. If it's out when I'm ready to build I'll certainly look at it though.

Exciting news.
 
I've also thought about building a pure gaming rig and going Core i9 9900K/9900KF, but I'm not sure I want to go that route. I could probably make that work, but right now I have more devices than that platform has lanes. I could make Ryzen 3000 work as it has everything I need. I need to benchmark the Ryzen 3000 and Core i9 9900K @ 4K and see if there is any difference at all. I doubt there is, but that would help make my decision easier.
 
I need to benchmark the Ryzen 3000 and Core i9 9900K @ 4K and see if there is any difference at all. I doubt there is, but that would help make my decision easier.

I'd read that writeup :p
 
I can barely imagine how to use 60 pcie3 lanes let alone 60 pcie4 Lanes. That's more bandwidth over pcie than the RAM can handle (DDR4@3200 or lower) that's just insane. ~120BG/s
 
You know how in the 2990WX, only 2 of the dies and thus half the cores have direct access to system RAM, compared to say EPYC 7601, which had 8 memory channels and all 4 dies had direct access to RAM? I wonder how Zen 2 Threadripper will turn out in that regard. 64-core Zen 2 EPYC has 8 freakin' chiplets. Oh wait, I seeee, it's the I/O die that connects to the 8 memory channels. So I assume then in Zen 2 Threadripper that the I/O die will just connect to the 4 memory channels. All the chiplets and thus all cores will get full access to those 4 memory channels through the I/O die. Pretty cool. Zen 2 is fun!
 
I can barely imagine how to use 60 pcie3 lanes let alone 60 pcie4 Lanes. That's more bandwidth over pcie than the RAM can handle (DDR4@3200 or lower) that's just insane. ~120BG/s

You wouldn't be trying to max out all the lanes at all times. Firstly, you'd have a mix of gen1, gen 2, gen3 and gen4 expansion boards, and it's not like they sit there pinning their full bandwidth at all times. Most loads over PCIe are very bursty. You just want more lanes so that you can add more expansion and not worry about not having enough. For most people its going to be for flexibility.

My Sandy-E 3930k has 40 lanes. I only use 33 of them, in a mix ranging from gen 1 to gen 3 as follows:

Slot 1: 16x, Gen 3, GPU
Slot 2: Empty (or GPU would drop to 8x)
Slot 3: 1x, Gen 1, Sound Card
Slot 4: 8x, Gen 2, Dual 10 Gig Ethernet
Slot 5: 4x, Gen 3, Samsung 970 EVO 1TB (In PCIe Slot adapter)
Slot 6: 4x, Gen 3, Intel SSD 750 400Gig (only PCIe SSD I can get to boot on my pre-NVME motherboard)

If I consolidate down to one NVMe SSD (maybe a 2TB model) I can still make this work on x570, as it has those extra lanes off of the chipset. Previous Ryzens just would not work for me.

I like the Threadripper approach. I'd rather have extra PCIe lanes I'm not using than not have enough when I want to install something.

My Corsair 750D case has 9 PCI slots. My ideal system would have some massive EATX+ motherboard with 9 slots, all 16x electrically going up to Gen 4, so that I have full flexibility and can add and remove whatever I want whenever I want.

Granted that would result in a ridiculously large CPU socket due to all th epins needed for those 144 PCIe lanes, but man would it be awesome.
 
You know how in the 2990WX, only 2 of the dies and thus half the cores have direct access to system RAM, compared to say EPYC 7601, which had 8 memory channels and all 4 dies had direct access to RAM? I wonder how Zen 2 Threadripper will turn out in that regard. 64-core Zen 2 EPYC has 8 freakin' chiplets. Oh wait, I seeee, it's the I/O die that connects to the 8 memory channels. So I assume then in Zen 2 Threadripper that the I/O die will just connect to the 4 memory channels. All the chiplets and thus all cores will get full access to those 4 memory channels through the I/O die. Pretty cool. Zen 2 is fun!

Yeah, my understanding is that uneven memory latency between CCX:es just isn't an issue anymore now with chiplets.

There will still be some residual issues when it comes to inter-CCX communication, as threads running on remote CCX's will take longer to communicate with. The good news is the Windows 1903 scheduler is supposedly more aware of this now, and tries to schedule threads that are related to each other on the same CCX, to avoid this issue.

It's an interesting problem, as from a thermal perspective, you'd want to spread your load out as much as possible, but from an inter-thread latency issue you'd want as much running on the same CCX as possible. The scheduler will have to try to guess which threads belong together, and which are fine to separate.
 
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