I agree with wanting an 'all or nothing' approach given that AMD went the software route for their mildly-heterogeneous architecture vs. say Intel with a hardware solution for their P- and E-cores.Yeah I've been waiting for CCDs to have more than 8 cores per CCD, so that we can see more than just 8 cores having access to the 3D cache. Now another thing I wouldn't mind seeing is 3D cache on both CCDs.
Kind of a poorly named conference, I think.Hot Chips
I would think the best way to do this is to oppose CCD scheduling to be akin to socket scheduling for multi socket systems. Then the OS could intelligently segregate load based on what is being ran across multiple CCX's more directly and not worry about thread scheduling between CCX's at all unless the load has more threads than a single CCX can provide.I agree with wanting an 'all or nothing' approach given that AMD went the software route for their mildly-heterogeneous architecture vs. say Intel with a hardware solution for their P- and E-cores.
Still think AMD needs to work the latency issue with multiple CCDs. They could address it directly, or they could improve operating system coordination for thread assignment, or come up with some other measure that is effective for software that will make use of the cores on multiple CCDs which is also sensitive to inter-core latency.