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An AMD EPYC Rome engineering sample (ZS1711E3VIVG5_24/17_N) has surfaced on SiSoftware in an announced Dell PowerEdge (R6515) server. The CPU flaunts 32 cores/64 threads with a base clock of 1.7 GHz (2.4 GHz boost).
Tom’s Hardware points out this is lower than the previous generation, but AMD may offset the regression by increasing IPC throughput.
The chip seemingly features a 1.7 GHz base clock, 2.4 GHz boost clock, 16MB of L2 cache and a doubling to 128MB of L3 cache. The "Z" prefix suggests that the leaked processor in question is a qualification sample (QS). Therefore, the specifications could be very close to the final product. That makes the relatively low clock speeds an interesting aspect, especially in comparison to the previous-gen 32-core EPYC 7601.
Tom’s Hardware points out this is lower than the previous generation, but AMD may offset the regression by increasing IPC throughput.
The chip seemingly features a 1.7 GHz base clock, 2.4 GHz boost clock, 16MB of L2 cache and a doubling to 128MB of L3 cache. The "Z" prefix suggests that the leaked processor in question is a qualification sample (QS). Therefore, the specifications could be very close to the final product. That makes the relatively low clock speeds an interesting aspect, especially in comparison to the previous-gen 32-core EPYC 7601.