Actually, here is some interesting information I was unaware of
courtesy of WikiChip:
So, process nodes were originally named after gate length.
This held up until 1997. At that point the gates actually shrunk FASTER than the names. At the time Intel hit their 45nm process, the gate length was actually 25nm, so they were using a higher number for their nodes than was accurate.
That's where further gate shrinkage did not work. Other features kept getting smaller, but gates kept the same size or got larger. 32nm actually had larger gates than 45nm.
Gates have not really shrunk since Intel's 45nm process (when they were 25nm in size), but all other features have kept shrinking and ocverall chips have become more and more dense, despite the gates staying at or above 25nm.
The part I don't understand is why the ITRS definition of a process node which is
"the smallest half-pitch of contacted metal 1 lines allowed in the fabrication process" can't still be used.
Unless I have misunderstood the terminology, this seems to not care about what feature you are talking about (gate or whatever) and is more concerned with the smallest feature a process can support, which seems like a very reasonable way of measuring a process.
The only reason fabs don't do this - I presume - is for marketing purposes.
So, I stand by my statement that marketers should be shot.
