AMD 9800X3D Has an Unlocked Multiplier According to Leaked Specs and a New Rumor Suggests That Its 3D V-Cache Is Layered Under the CCD

[Zarathustra]

I don't care where they put it. Just give me two of them on the 9950X3D. Please, AMD. I beg you.

This 100%. If you're still stuck on 8 cores per CCD, then at least give me 3D cache on both/all CCDs.

I wonder how well that would even work.

You'd have to do a very good job of workload planning to avoid huge latency hits when CCD 0 might need to access something in CCD1's vcache.

And in more random loads you may just have to duplicate the entire cache content on both CCD's, which would be very inefficient.

It winds up being a whole new NUMA problem that adds more complexity to scheduler design.

 

[LeRoy_Blanchard]

I have shell scripts that taskset pins tasks to specific cores and CCDs so cross CCD communication over the infinity fabric doesn't occur. It's the same "problem" for all AMD Ryzen, EPYC and Thread ripper lineups with more than 1 CCD and/or more than one CCX within a CCD.