Nobody knows what the bandwidth or latency would be like on a modern L4 cache implementation. Also you do not want to be on the hook for implementing eDRAM on some/all of your consumer CPUs when the memory manufacturers are busy focusing on HBM production for some company that is not you.512MB eDRAM would've had much better latencies AND bandwidth than at least 80% of worldwide DDR5 RAM sales. They just needed to iterate on the technology with incremental generational refinements.
edit: I'm assuming eDRAM dice would be coming from RAM manufacturers, but if Intel could fab it themselves on one of their own processes then maybe it wouldn't be so bad.