Intel Nova Lake-S Rumors: Seven SKUs Featuring Up to 52 Cores, 65W-150W TDP, Support for DDR5-8000 MHz with 36x PCIe 5.0 Lanes

[Peter_Brosdahl]

Rumors have been circulating about Intel's Nova Lake-S platform, and it looks like the Arrow Lake successor will feature many improvements.

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[DrezKill]

Oh for f*ck's sake, a THIRD type of core?!

Yyyeeeaaahhh, I'm sure this is not gonna confuse the f*ck outta OS thread schedulers, games, and other individual software. Cuz it's not like the hybrid P-cores + E-cores don't already do that. Software developers that get deep into hardware are gonna love coding for these abominations.

 

[LazyGamer]

Yyyeeeaaahhh, I'm sure this is not gonna confuse the f*ck outta OS thread schedulers, games, and other individual software. Cuz it's not like the hybrid P-cores + E-cores don't already do that. Software developers that get deep into hardware are gonna love coding for these abominations.

Do we know if these cores are a different architecture than the E-cores? My understanding (which may be obsolete) was that they were E-cores, just on the chipset instead of on the CPU. Much lower power but no different from an execution standpoint.

Otherwise, I thought we got the E-core / P-core schedular stuff fixed during the 12th generation?

 

[Grimlakin]

Oh for f*ck's sake, a THIRD type of core?!

Yyyeeeaaahhh, I'm sure this is not gonna confuse the f*ck outta OS thread schedulers, games, and other individual software. Cuz it's not like the hybrid P-cores + E-cores don't already do that. Software developers that get deep into hardware are gonna love coding for these abominations.

Job security?

Do we know if these cores are a different architecture than the E-cores? My understanding (which may be obsolete) was that they were E-cores, just on the chipset instead of on the CPU. Much lower power but no different from an execution standpoint.

Otherwise, I thought we got the E-core / P-core schedular stuff fixed during the 12th generation?

The latency in pulling data from Cache transitioning from chipset to CPU alone will be huge. The big win for E-cores as I understand it is offloading less demanding processes. This will need another level of consideration to happen efficiently if the cores are on the chipset as opposed to the CPU die. At least as I understand threading and processing. It would make the dual CCD latency issue on early ryzen CPU's seem FAST.

 

[LazyGamer]

I don't think low power states are really latency sensitive?