Ryzen 9 9950X3D2 Dual Edition is Official: AMD Puts 3D V-Cache on Both Chiplets, Launches April 22

[David_Schroth]

The chip enthusiast community has been waiting on this one since last year, and AMD finally pulled the trigger today. The Ryzen 9 9950X3D2 Dual Edition is officially real, officially named, and officially coming April 22, 2026. It is the first desktop processor to place AMD’s 3D V-Cache stacking on both core complex dies simultaneously, […]

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[Grimlakin]

Not gonna lie if fhe numbers rumored are right I kinda want to flip amd the Ole bird for not just doing this with the 9950x3d. Sigh...

 

[Skillz]

Man, RAM prices suck. That's all I got to say.

 

[Stoly]

while this sounds great on paper, I don't think there will meaningful real world benefits.

 

[Peter_Brosdahl]

Keeping a keen eye on this but still waiting for that Zen6 part with 10 or 12 or more cores but I have a feeling we won't get anything official until the fall or maybe even CES 27.

 

[LazyGamer]

while this sounds great on paper, I don't think there will meaningful real world benefits.

Well, not in gaming at least. Or raw compute.

 

[igor_kavinski]

while this sounds great on paper, I don't think there will meaningful real world benefits.

It will help. The dual CCD X3D nutsack will finally be balanced.

Because that's what the original plan was before someone thought, ph wait, let's make double the money! https://www.tomshardware.com/news/a...mb-of-l3-cache-per-chip-15-gaming-improvement

This is the way.

 

[Skillz]

while this sounds great on paper, I don't think there will meaningful real world benefits.

Proving numbers (well technically finding them, but they're not like, missing or hiding but anyway) are prime that are millions of digits long where their FFT length is greater than 32MB (The amount of data that the process needs to do calculations) will be able to still fit within' the L3 cache of the processor for both CCXs. This will allow those calculations to happen at a faster rate. Compared to those sized prime searches needing to utilize the RAM of the host system doing the calculations.

Server grade hardware for Intel has CPUs with large amounts of unified cache, but AMD chiplet designs limits the amount of fast access to the L3 within' a CCX to whatever size that L3 cache domain is. Sure some EPYCs have all their CCX's with this technology, but for the consumer parts that are more affordable for the mass being able to buy a consume CPU that double's this ability will be significant for that specific, real world, use case.

Real world benefit.