AMD Zen 6 Discussion

moinmoin said:
They have an office in Taiwan, but not in China, so I'd guess the former.
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Could be Vietnam or India. In any case they're probably getting hardware from some of the same industrial districts as GMK.
 
Any news on the chip interconnect used for Zen 6 on desktop? Are we getting the rumored more advanced packaging?
 
One of the latest rumor theories is that AMD is waiting for Intel's refresh launch/announcements to finish and then they might start giving some updates.
 
Peter_Brosdahl said:
One of the latest rumor theories is that AMD is waiting for Intel's refresh launch/announcements to finish and then they might start giving some updates.
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I'm not sure about that. Both AMD and Intel follow fairly consistent schedules for releasing chipperies, so I'm not expecting much from a surprise perspective -

Intel - Typically launches a new -S* generation end of Q3/beginning of Q4 with 3-4 -K processors, then fill in the rest of that generation/socket with lower power stuff around CES. Then for Computex, new mobile chips.

AMD - Zen has been launching a new generation about every 2 years, mostly around Computex time (for the main 4 or so X varieties) for the announcement with availability in Q3. X3D chips have been following 6-12 months after. Then the rest of the family is filled out over time with lower wattage chips.

So what does that mean I expect based on history? Intel will likely launch an Arrow Lake-S Refresh soon and Zen 6 will be announced at Computex 2026 with availability in Q3 2026. If AMD really wanted to pull it forward, we might see something at CES 2026, but I also doubt it.

* -S being the desktop class CPUs for a particular code name, most recently, Arrow Lake-S, aka, Core Ultra 285K, et. al.
 
As far as clockspeeds I would be very surprised if Zen 6 will sustain 6GHz under load (like 8 or 10 cores loaded up) much less 7GHz. Not that I'm not hoping for it, but 6GHz has been a "speed barrier" for quite some time. Intel broke it briefly with Raptor Lake only to have degradation issues.
 
Hulk said:
As far as clockspeeds I would be very surprised if Zen 6 will sustain 6GHz under load (like 8 or 10 cores loaded up) much less 7GHz. Not that I'm not hoping for it, but 6GHz has been a "speed barrier" for quite some time
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6GHz is more or less 'right there'; it really seems that AMD and Intel have other fish to fry before doing the engineering to make that possible, because small bumps in clockspeed are fairly meaningless now. Might actually be detrimental if they make sacrifices to get there i.e. adding pipeline stages a la Netburst.

Hulk said:
Intel broke it briefly with Raptor Lake only to have degradation issues.
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Well, the P-cores could handle that and more, no question. They're stout. Raptor Lake's problem seemed to be rather the bus that shared its voltage plane with the CPU cores, so that when a P-core or two would jump up in clockspeed and require a burst of juice, even while the rest of the CPU was using much less power, that bus could be damaged. And once that degradation hit a tipping point it was game over unfortunately.

But Intel could absolutely build a solid 6+GHz part too, if that were a design goal.


I'd say that it'd be easier for Intel to push clockspeeds than AMD, given currently released products, but realistically either could do a 7GHz SKU if that was an engineering goal they wanted to hit.

The bigger question is whether it'd make a difference vs. putting their resources into increases in IPC or reducing latency instead.
 
Intel is currently constrained by process wrt clockspeeds. 18a is not suitable for high clockspeed designs, and anything else they have is old and as such is not even remotely competitive from TSMC's latest. 18ap may fix that in 2027, we will have to wait and see.

Using TSMC silicon is problematic since they are paying for both their own node development but also buying wafers from TSMC for products like Arrow Lake and (later) Nova Lake. Previously Intel could defray the cost of node development by selling products across their entire lineup, but now they can only do so with enterprise chips that still utilize internal nodes, as well as the remaining consumer offerings that do the same (Panther Lake, Arrow Lake-U/Meteor Lake).

It is not clear whether AMD's existing designs or immediate future designs are actually design-limited when it comes to higher clockspeeds. It may simply be a matter of process and v/f curves + thermals.
 

AMD aims for biggest laptop push with FP10 socket — to support 4 different zen 6 SoC configs​


it should support 4 different CPU configs
  1. Medusa Point 1 (MDS-1) — mainstream laptops
    1. 4p + 4c + 2lp cpu config
    2. 8 CU RDNA 4M (rdna 3.5 with a few matrix multiply features of rdna 4)
    3. TSMC 3nm unified SoC
  2. Medusa Point 1 High (MDS-1 Hi) — premium laptops (to be paired with Nv dgpus)
    1. extra 12p core zen 6 ccd
    2. TSMC 2nm for extra CPU CCD
  3. Medusa Point 2 (MDS-2) — budget laptops
    1. 2p? + 2c? + 2lp cpu config
    2. 4CU or 2CU RDNA 4M
    3. TSMC 3nm unified SoC
  4. Medusa Premium (MDS-P / Medusa Halo mini / Z3 Extreme) — gaming devices (laptops, tablets, handhelds, steam machine competitors & the XBOX series S2)
    1. 4p + 8c + 2lp (similar to Magnus / Helix)
    2. 100 TOPS NPU (similar to Magnus / Helix)
    3. 24 CU RDNA 5 AT4 GPU chiplet (1/3rd GPU power of 68 CU Magnus / Helix)
    4. both CPU soc & additional AT4 GPU chiplet are on TSMC 3nm
https://twitter.com/x/status/2092552096960704584
 
Marees said:

AMD aims for biggest laptop push with FP10 socket — to support 4 different zen 6 SoC configs​


it should support 4 different CPU configs
  1. Medusa Point 1 (MDS-1) — mainstream laptops
    1. 4p + 4c + 2lp cpu config
    2. 8 CU RDNA 4M (rdna 3.5 with a few matrix multiply features of rdna 4)
    3. TSMC 3nm unified SoC
  2. Medusa Point 1 High (MDS-1 Hi) — premium laptops (to be paired with Nv dgpus)
    1. extra 12p core zen 6 ccd
    2. TSMC 2nm for extra CPU CCD
  3. Medusa Point 2 (MDS-2) — budget laptops
    1. 2p? + 2c? + 2lp cpu config
    2. 4CU or 2CU RDNA 4M
    3. TSMC 3nm unified SoC
  4. Medusa Premium (MDS-P / Medusa Halo mini / Z3 Extreme) — gaming devices (laptops, tablets, handhelds, steam machine competitors & the XBOX series S2)
    1. 4p + 8c + 2lp (similar to Magnus / Helix)
    2. 100 TOPS NPU (similar to Magnus / Helix)
    3. 24 CU RDNA 5 AT4 GPU chiplet (1/3rd GPU power of 68 CU Magnus / Helix)
    4. both CPU soc & additional AT4 GPU chiplet are on TSMC 3nm
https://twitter.com/x/status/2092552096960704584
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additional m/b sockets

  1. Medusa Point 3 (MDS-3 / BumbleBee / BB / Baby Medusa) — entry level
    1. 2p + 2c + 2lp cpu config
    2. 2 CU RDNA 4m
    3. unified TSMC 3nm SoC
  2. Medusa Halo (MDS-H) — super premium, AI use cases
    1. upto 2 CPU ccds (total 24 or 26 cores)
    2. 384 bit lpddr6 unified memory — can go up to 512 GB
    3. 48 CU RDNA 5 AT3 GPU (double the GPU power of AT4)
    4. cpu ccds could be mix of 3nm & 2nm
    5. AT3 GPU ccd on 3nm
    6. FP12 socket
 
Nice I appreciate that kind of tech presentation. Now where's the old pc magazine discussion on cores and optimizations?
 
www.techpowerup.com

AMD Zen 6 Technical Deep Dive

AMD's new Zen 6 architecture is more than a routine refresh, with a 12-core CCD, 4 MB of L3 per core, and a much bigger execution window that should finally let AMD's wider design shine. AMD focused on sharing the server details, but we'll do our best to translate this to Ryzen and gaming, too.
www.techpowerup.com www.techpowerup.com

12 cores per CCD, at last!

Also while I don't care for E-cores, it sounds like Zen 6 will be doing it much better than Intel has thus far, with Zen 6C.

2nm TSMC node, still 8-channel RAM setup, oh wow there are two I/O dies?! And PCI-Express 6.0 too.
 
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