Gotta know supply to gauge demand...Also like I said in the other thread, the ultra 9 and 5 are already sold out at some outlets around here. intel still going strong (or no stock to speak off)
I think they can. How they would be able to mitigate this is unclear to me but this is the type of thing Intel is typically good at engineering their way through historically. Generally speaking, Intel's CPU's have not been effected by latency to the same degree as AMD's. AMD for one reason or another has always dealt with that to some degree. AMD's answer for the most part was simply to throw L3 cache at the problem which doesn't work in all scenarios.@Brent_Justice - what I'm seeing about is that by decoupling the memory controller from the compute die, Intel has added latency to main memory access. Do we know if this is reflected in say AIDA64?
@Dan_D - looks like we're going to have to see if Intel can overcome the above latency issue the same way AMD did when they went to chiplets with Zen.
AMDs use of stacking for the L3 cache on a CCD, which in turn they can use for gaming SKUs as well as enterprise (which they originally created them for), is genius.Though throwing L3 cache at the problem is a simple fix, but its a costly one.
I think they can. How they would be able to mitigate this is unclear to me but this is the type of thing Intel is typically good at engineering their way through historically. Generally speaking, Intel's CPU's have not been effected by latency to the same degree as AMD's.
I'm not sure that this is even possible. I think there are probably scenarios where simply adding cache doesn't help.AMDs use of stacking for the L3 cache on a CCD, which in turn they can use for gaming SKUs as well as enterprise (which they originally created them for), is genius.
Imagine slow(er) Zen 3 and Zen 4 cores (both clockspeed and IPC vs. Alder/Raptor P-cores) not only outrunning them but also doing so at 1/2 the power draw for gaming.
Now imagine Intel P-cores backed up by enough L3 cache to make memory latency irrelevant.
Well, AMD had an integrated memory controller since the Athlon 64 days. However, Intel's Core 2 Duo/Core 2 Quad were the last CPU's to have an off-die memory controller. Though it was in the chipset at the time and not anywhere on the CPU itself.I think Intel needs to copy AMD here (or emulate? imitate?) and find a way to get that cache in a die with broader market appeal (i.e. also usable in Xeons). Their chiplet setup should enable them to do so.
One thing that's been sticking in my mind with the Arrow Lake release is that this is the first time Intel has decoupled their memory controller from their compute dies since... Core 2? At least in the consumer space (so not talking about buffered DIMMs). AMD did with Zen 2 IIRC. Intel has been using IMCs since Lynnfield in the i7 870 from 2009, 15 years ago!
Not competitive, high price, a short lived platform and Win 11 is a mess. Nothing ever works as intended at launch. What is wrong with these companies? Fumbling the ball at the 1-yd line seems to be the norm. Bush league overall...
@Brent_Justice - what I'm seeing about is that by decoupling the memory controller from the compute die, Intel has added latency to main memory access. Do we know if this is reflected in say AIDA64?
Thanks, @Brent_Justice for the very detailed review of these CPUs and extra testing with both power modes. It's a shame that APO isn't supported for the games reviewed, especially since they are popular titles that users are likely to have in their libraries. I wonder if Intel will be able to provide updates later on which might improve those results. Really interesting how CB2077 has a prioritize P-core option that only further proved there are other potential gains to be had.
A lot to unpack with these and obviously Intel is experimenting with a number of strategies with them.